1. Field of the Invention
The present invention relates to a method for forming a dual damascene structure. In particular, the present invention relates to a method for forming a dual damascene structure by calculating a periodic parameter.
2. Description of the Prior Art
In the manufacturing process of semiconductors, metals are used for the formation of interconnect of elements. Aluminum used to be used for the formation of interconnect of elements. However, with the shrinkage of the element critical dimension (CD) and the obvious behavior of electromigration, aluminum is less and less qualified to be used for the formation of interconnect of elements. Currently, copper is generally used to replace aluminum for the formation of interconnect of elements because copper has a much lower electric resistance, better RC delay time and weaker behavior of electromigration.
In addition to the much lower electric resistance, the reasons why copper is chosen to replace aluminum resides in that copper has a higher melting point and much higher thermal conductivity coefficient than aluminum does, so copper may form thin films by dry process such as chemical vapor deposition plus physical chemical vapor deposition or by wet process such as physical chemical vapor deposition to form seed layer plus electroplating. For such reasons, copper is highly appreciated in the multilayer metal interconnect in the coming generations.
However, there are severe problems coming with the usage of copper to replace aluminum for the formation of interconnect of elements, which are highly incompatible with the conventional Al process, i.e. the copper wires cannot be patterned by the conventional methods used to pattern the Al wires. On one hand, copper fails to form highly volatile chlorides so the dry etching techniques used in the conventional Al process cannot be applied in the copper process. On the other hand, because the wet etching of copper suffers severe under-cut, the narrower the line width the severer the problem, the only practical method available on the production line is the damascene process.
The feature of the damascene process is that copper is deposited in the openings such as trenches or vias in the dielectric layers. The trenches and vias are usually defined in the dielectric layer by lithographic and etching steps. On one hand, the damascene process includes the single damascene process and the dual damascene process. Only one of trenches and vias is formed in the single damascene process. In the dual damascene process, trenches and vias are overlapped to form in the same position. On the other hand, based on the etching fashions of the dielectric layers, the damascene technique may be classified into various types such as “trench first” or “via first,” each with its different technical problems.
FIGS. 1-5 illustrate an example of forming a dual damascene structure in the prior art. Taking the damascene process for forming vias for example, first a substrate 101 is provided. A layer of meal 102 is already formed in the substrate 101 in advance. There is an interlayer dielectric layer 103 with a thickness A on the substrate 101. Second, the vias for the damascene structure are required to be formed in the interlayer dielectric layer 103 as the bridge of the electric connections for the metal layer 102. The method for forming the vias for the damascene structure is that, as shown in FIG. 2, a layer of photo resist 104 is first formed on the interlayer dielectric layer 103. Then, as shown in FIG. 3, the photo resist layer 104 is patterned to form the pattern opening 105. Later, the interlayer dielectric layer 103 is etched using the patterned photo resist layer 104 as an etching mask to construct the via 106 exposing the substrate 101 in the interlayer dielectric layer 103. Please note that the photoresist is consumed during the etching of the interlayer dielectric layer 103, so the thickness of the photo resist layer 104 in FIG. 3 and in FIG. 4 is different.
Although the interlayer dielectric layer 103 is indeed at least partially removed by the etching, not all of the vias 106 may expose the substrate 101 due to reasons such as high aspect ratio and lithographic and etching technical problems. Once the via 106 does not expose the substrate 101, as shown in FIG. 4, no effective metal interconnect structure 107 to the metal layer 102 can be formed even if copper is successfully filled in the via 106. The elements in the semiconductor therefore fail due to lack of proper electric connections, as shown in FIG. 5.
Accordingly, a method for forming a dual damascene structure is needed in order to thoroughly remove all the materials of the interlayer dielectric layer in the vias during the etching of the interlayer dielectric layer so that an effective metal interconnect structure to the metal layer can be formed to ensure good electric connections between the elements in the semiconductor.